1. Field of the Invention
The present invention relates to an integrated, programmable logic array having a product matrix, wherein control lines for true and inverted input variables are linked according to a programming rule with product lines for the formation of product signals, the linkage being with the assistance of semiconductor logic elements controlled by the input variables in such a manner that specific input variables generate the higher or the lower of two binary signal levels on product lines or do not influence the product lines at all, and having a sum matrix wherein the product lines are linked according to a further programming rule with sum lines for the formation of sum signals, the linkage being with the assistance of semiconductor logic elements controlled by the product lines in such a manner that specific product signals generate the higher or lower binary signal level on sum lines or do not influence sum lines at all.
2. Description of the Prior Art
Logic arrangements of the type set forth above are also known by the abbreviation PLA or the abbreviation FPLA, and are generally known in the art, for example, from the publications "Der Elektroniker", No. 3, 1981, pp. 44-48; "Valvo-Brief", Oct. 25, 1976, pp. 1-3; and "Electronic Design", Vol. 29, No. 4, 1981, pp. 121-124, all of which are fully incorporated herein by this reference. In such logic arrays, input stages connect the original input variables through on control lines of a product matrix in their true form and inverted form. Semiconductor elements are disposed at some of the intersections of the control lines with the product lines of the matrix, signal potentials on the product lines being controllable with the assistance of the semiconductor elements by way of the input variables. Corresponding logic elements are absent at other intersections or are suppressed. The product lines form the input lines for a sum matrix in which they intersect with sum lines. Here, also, the logic elements are generally effective only for a portion of the intersections. The signals existing on the same lines are amplified in output drivers and are sometimes inverted.
The logic functions of the product matrix and of the sum matrix must be matched to one another. Instead of an AND operation with a following OR operation, for example, a NOR operation can be formed twice (cf. Electronic Design supra.
In the manufacture of integrated, programmable logic arrays, logic or, respectively, switching elements are frequently first disposed at all intersections of the matrices, these then being partially suppressed in accordance with the programming rule by subsequent interruption of suitable connections, for example, by fusing fusable links.
Depending on the size of the two matrices of a programmable logic array, a more or less great multitude of complex logical functions can be realized, their type being determined by the programming.
Particularly in sequential circuits wherein the sum lines are, for example, connected to the data inputs of D flip-flops, it is frequently desirable to load an external datum into the flip-flops independently of the variables applied to the inputs of the logic array. Such a possibility also offers advantages in testing the sequential circuits.
Such expansions were heretofore possible only with a high additional surface expense for the matrices or by way of additional, external logic elements.